The present invention disclosed herein relates to an electronic device, and more particularly, to a memory system.
Semiconductor memory devices may be largely classified into volatile semiconductor devices and non-volatile semiconductor memory devices. The volatile semiconductor memory device may have an advantage in that read and write operations are performed at a high speed, but may have a disadvantage in that its stored contents disappear if there is no external power supply. In contrast, the non-volatile semiconductor memory device may retain its stored contents regardless of power supply applied thereto. The non-volatile semiconductor memory device may include a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), and an electrically erasable programmable read-only memory (EEPROM).
In general, it may be difficult for general users to update memory contents since a system itself may be restricted for performing erase and write operations on the MROM, PROM, and EPROM. In contrast, since the EEPROM is capable of performing erase and write operations electrically, it may realize increased applications of system programming (which requires continuous updating) and/or auxiliary memory devices. This may be especially true since a flash EEPROM may have a higher integration degree compared to a typical EEPROM. In this regard, the EEPROM may provide significant advantage regarding applications in high capacity auxiliary memory devices. A NAND-type flash EEPROM (hereinafter, referred to as a NAND flash memory) among flash EEPROMs may have a higher integration degree than other flash EEPROMs.
As a demand for the high integration degree of memory devices has increased, multi-bit memory devices storing a multi-bit in one memory cell is extensively used. Memory cells of the multi-bit memory device may be controlled with a dense interval between threshold voltage distributions. That is, data retention characteristic and the number of program/erase cycles (or durability) without quality deterioration may be an important concern as related to data reliability. However, a threshold voltage of a memory cell may change due to various factors. For example, electric charges (or, electrons) stored in a floating gate may leak through thermionic emission and charge diffusion (which are caused by a defective insulation layer and various fail mechanisms such as ion impurities and program disturb stress). This may cause a shift of a threshold voltage. If a floating gate stores charges gradually when a control gate is in a state where a predetermined voltage (for example, a power voltage or a read voltage) is maintained, charge acquisition effect may occur due to read disturb. This may increase a threshold voltage. Accordingly, threshold voltage distributions of memory cells may gradually broaden due to charge loss and charge acquisition. This threshold voltage range expansion may result in increased errors in read data. Therefore, error control techniques may be beneficial.